Japanese Laid-Open Patent Publication No. 2003-318398 discloses a semiconductor device having an N−-type polycrystalline silicon region, which is formed and adjoined to a main surface of a semiconductor substrate. The semiconductor substrate has an N+-type silicon carbide substrate on which an N−-type silicon carbide epitaxial region is formed. In this semiconductor device, the N−-type silicon carbide epitaxial region and the N−-type polycrystalline silicon region are hetero-adjoined to each other. Further, a gate electrode is formed adjacent to a heterojunction of the N−-type silicon carbide epitaxial region and the N−-type polycrystalline silicon region by using a gate insulation layer. The N−-type polycrystalline silicon region is connected to a source electrode through a source contact hole formed in an interlayer dielectric, A drain electrode is formed on the other surface of the N−-type silicon carbide substrate.
Such a semiconductor device functions as a switch by controlling an electric potential of the gate electrode when the source electrode is grounded and a predetermined positive electric potential is applied to the drain electrode. That is, when the gate electrode is grounded, a reverse bias is applied to the heterojunction of the N−-type polycrystalline silicon region and the N−-type silicon carbide epitaxial region such that no electric current flows between the drain and the source electrodes. However, when a predetermined positive voltage is applied to the gate electrode, a gate electric field is applied to the heterojunction interface of the N−-type polycrystalline silicon region and the N−-type silicon carbide epitaxial region. Since the thickness of an energy barrier (ΔEc) defined by the heterojunction of a gate oxide film interface is reduced, the current can flow between the drain electrode and the source electrode. In addition, this semiconductor device uses the heterojunction as a control channel for interrupting and conducting the current. Thus, the thickness of a hetero barrier functions as a length of the channel, and conductivity with a low resistance can be obtained. A resistance can be lowered as the intensity of the gate electric field increases in the heterojunction interface of the N−-type polycrystalline silicon region and the N−-type silicon carbide epitaxial region where the gate electrode is adjoined using the gate insulation layer.